the gm71v(s)18160c/cl is the new generation dynamic ram organized 1,048,576 x 16 bit. gm71v(s)18160c/cl has realized higher density, higher performance and various functions by utilizing advanced cmos process technology. the gm71v(s)18160c/cl offers fast page mode as a high speed access mode. multiplexed address inputs permit the gm71v(s)18160c/cl to be packaged in standard 400 mil 42pin plastic soj, and standard 400mil 44(50)pin plastic tsop ii. the package size provides high system bit densities and is compatible with widely available automated testing and insertion equipment. description features * 1,048,576 words x 16 bit organization * fast page mode capability * single power supply (3v+/-0.3v) * fast access time & cycle time ( unit: ns) pin configuration 1,048,576 words x 16 bit cmos dynamic ram gm71vs18160cl * low power active : 684/612/540/468mw (max) standby : 7.2mw (cmos level : max) 0.54 mw (l-version : max) * ras only refresh, cas before ras refresh, hidden refresh capability * all inputs and outputs ttl compatible * 1024 refresh cycles/16ms * 1024 refresh cycles/128ms (l-version) * self refresh operation (l-version) * battery back up operation (l-version) * 2 cas byte control gm71v(s)18160c/cl-5 gm71v(s)18160c/cl-6 gm71v(s)18160c/cl-7 t rac t cac t rc t pc 50 60 13 15 90 110 35 40 70 18 130 45 ( top view) gm71v18160c 42 43 44 45 46 40 41 33 30 31 32 27 28 29 26 34 35 36 47 48 49 50 nc nc v ss i/o15 i/o14 i/o13 i/o12 i/o11 i/o10 i/o9 i/o8 v ss lcas ucas oe a8 a7 a6 a5 a4 v ss a9 v ss i/o15 i/o14 i/o13 i/o12 38 39 40 41 42 i/o11 i/o10 i/o9 i/o8 nc 32 33 34 35 36 v ss 37 lcas ucas oe 29 30 31 a9 a8 a7 26 27 28 a6 a5 a4 23 24 25 v ss 22 11 1 2 3 4 5 7 8 9 10 6 15 16 17 18 19 20 21 22 23 24 25 nc nc i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 v cc nc we ras a11 a10 a0 a1 v cc v cc a2 a3 44(50) tsop ii v cc i/o0 i/o1 i/o2 i/o3 1 2 3 4 5 i/o4 i/o5 i/o6 i/o7 nc 7 8 9 10 11 v cc 6 nc we ras 12 13 14 nc nc a0 15 16 17 a1 a2 a3 18 19 20 v cc 21 42 soj rev 0.1 / apr ? 01
gm71vs18160cl gm71v18160c rev 0.1 / apr ? 01 ordering information type no. access time package gm71v(s)18160cj/clj -5 gm71v(s)18160cj/clj -6 gm71v(s)18160cj/clj -7 50 ns 60ns 70ns 400 mil 42 pin plastic soj 50 ns 60ns 70ns 400 mil 44(50) pin plastic tsop ii gm71v(s)18160ct/clt -5 gm71v(s)18160ct/clt -6 gm71v(s)18160ct/clt -7 pin description pin function pin function a0-a9 a0-a9 i/o0-i/o15 ras we v cc v ss nc address inputs refresh address inputs data input/ data output row address strobe read/write enable power (+3.3v) ground no connection ucas, lcas column address strobe oe output enable absolute maximum ratings* note: operation at or above absolute maximum ratings can adversely affect device reliability. symbol parameter rating unit t a t stg v in/out v cc i out 0 ~ 70 -55 ~ 125 -0.5 ~ vcc +0.5 (<=4.6v(max)) -0.5 ~ 4.6 50 ambient temperature under bias storage temperature voltage on any pin relative to v ss supply voltage relative to v ss short circuit output current v v ma p d 1.0 power dissipation w c c
gm71vs18160cl gm71v18160c rev 0.1 / apr ? 01 truth table ras lcas ucas we oe h l l l d h l h d h h l d h h h d d l l output open valid valid valid lower byte upper byte word operation standby ras-only refresh cycle read cycle l l l l l l h l h early write cycle l h l l h open open open l l l l undefined delayed write cycle l l l h h h to l l cbr refresh or self refresh (l-series) h to l h l h to l l l notes 1,3 1,3 1,3 1,3 1,3 1,2,3 1,2,3 1,3 lower byte upper byte word lower byte upper byte word lower byte upper byte word undefined undefined open open open open open valid valid valid word word word word read-modify -write cycle read cycle (output disabled) d d h to l h to l h to l l l l l l l l h l l l l h d d l h h h h l d d d d d d l to h l to h l to h l l l l recommended dc operating conditions (t a = 0 ~ + 70c) symbol parameter unit v cc v ih v il supply voltage input high voltage input low voltage v v v max 3.6 v cc + 0.3 0.8 typ 3.3 - - min 3.0 2.0 -0.3 note: all voltage referred to vss . the supply voltage with all vcc pins must be on the same level. the supply voltage with all vss pins must be on the same level. note: all voltage referred to vss . the supply voltage with all vcc pins must be on the same level. the supply voltage with all vss pins must be on the same level. notes: 1. h: high (inactive) l: low(active) d: h or l 2. t wcs >= 0ns early write cycle t wcs <= 0ns delayed write cycle 3. mode is determined by the or function of the ucas and lcas. (mode is set by earliest of ucas and lcas active edge and reset by the latest of ucas and lcas inactive edge.) however write operation and output high-z control are done independently by each ucas,lcas. ex) if ras = h to l, ucas = h, lcas = l, then cas-before-ras refresh cycle is selected.
gm71vs18160cl gm71v18160c rev 0.1 / apr ? 01 dc electrical characteristics (v cc = 3.3v+/-0.3v, vss = 0v, t a = 0 ~ 70c) symbol parameter note v oh v ol output level output "h" level voltage (i out = -2 ma ) unit v v max v cc 0.4 min 2.4 0 output level output "l" level voltage (i out = 2 ma ) i cc1 operating current average power supply operating current (ras, ucas or lcas cycling : t rc = t rc min) i cc2 standby current (ttl) power supply standby current (ras, ucas, lcas = v ih , d out = high-z) i cc3 ras only refresh current average power supply current ras only refresh mode ( t rc = t rc min) i cc4 i cc5 standby current (cmos) power supply standby current (ras, ucas or lcas >= v cc - 0.2v, d out = high-z) i cc6 cas-before-ras refresh current ( t rc = t rc min) i l(i) ua 10 -10 i l(o) ua 10 -10 input leakage current any input (0v <= v in <= 4.6v) output leakage current (d out is disabled, 0v <= v out <= 4. 6v) fast page mode current average power supply current fast page mode ( t pc = t pc min) i cc7 i cc8 battery back up operating current (standby with cbr refresh) ( t rc =125us , t ras <= 0.3 us, d out = high-z) 400 - 4,5 ua i cc9 ua self-refresh mode current (ras, ucas or lcas<=0.2v , d out = high-z) 250 - 5 note: 1. i cc depends on output load condition when the device is selected. i cc (max) is specified at the output open condition. 2. address can be changed once or less while ras = v il . 3. address can be changed once or less while lcas and ucas = v ih . 4. ucas = l (<=0.2) and lcas = l (<=0.2) while ras = l (<=0.2). 5. l-version. ma 5 - 1 standby current ras = v ih u cas, lcas = v il d out = enable ma 2 - ma 1 - 150 - ua ma 190 - 50 ns 60 ns 70 ns 170 150 - 1, 2 - ma 2 ma 1, 3 - 190 - 50 ns 60 ns 70 ns 170 150 - - 185 - 50 ns 60 ns 70 ns 165 145 - ma 190 - 50 ns 60 ns 70 ns - - 170 150 5
gm71vs18160cl gm71v18160c rev 0.1 / apr ? 01 read, write, read-modify-write and refresh cycles (common parameters) capacitance (v cc = 3.3v+/-0.3v, t a = 25c) symbol parameter note c i1 c i2 c i/o input capacitance (address) input capacitance (clocks) output capacitance (data-in/out) 1 1 1, 2 unit pf pf pf max 5 7 7 min - - - note: 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. ucas and lcas = v ih to disable d out . ac characteristics (v cc = 3.3v+/-0.3v, t a = 0 ~ 70c, note 1, 2, 18, 19, 20) test conditions input rise and fall times : 5 ns output timing reference levels : 0.8v, 2.0v input timing reference levels : 0.8v, 2.0v output load : 1ttl gate + c l (100 pf ) (including scope and jig) symbol parameter note max unit min max min max min t rc random read or write cycle time 90 - 110 - 130 - t rp ras precharge time 30 - 40 - 50 - t ras ras pulse width 50 10,000 60 10,000 70 10,000 t cas cas pulse width 10,000 10,000 10,000 15 18 t asr row address set up time 0 - - - 0 0 t rah row address hold time 8 - - - 10 10 t asc column address set-up time 0 - - - 0 0 t cah column address hold time - - - 10 15 t rcd ras to cas delay time 18 45 45 52 20 20 3 t rad ras to column address delay time 13 30 30 35 15 15 4 t rsh ras hold time 13 - - - 15 18 t csh cas hold time 50 - - - 60 70 t crp cas to ras precharge time 5 - - - 5 5 t t transition time (rise and fall) 3 50 50 50 3 3 7 t dzo oe delay time from d in 0 - - - 0 0 t dzc cas delay time from d in 0 - - - 0 0 gm71v(s)18160 c/cl-5 oe to d in delay time 13 - - - 15 18 5 6 6 t cp cas precharge time 8 - 10 - 10 - t odd gm71v(s)18160 c/cl-6 gm71v(s)18160 c/cl-7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13 8 24 21 21 22 23
gm71vs18160cl gm71v18160c rev 0.1 / apr ? 01 read cycle write cycle symbol parameter note max unit min max min t rac - 60 - 70 t cac - 15 - 18 t aa - 30 - 35 t rcs 0 - 0 - t rch 0 - - 0 8,9 9,10,17 9,10,17 - 15 - 18 9,25 12,22 gm71v(s)18160 c/cl-6 t oac gm71v(s)18160 c/cl-7 t rrh 5 - - 5 12 t ral 30 - - 35 t off 15 15 13 - - t cal 30 - - 35 t clz 0 - - 0 t oez 15 15 13 - - t oh 3 - - 3 t oho 3 - - 3 t cdd 15 - - 18 5 max min - 50 - 13 - 25 0 - 0 - - 13 gm71v(s)18160 c/cl-5 5 - 25 - 13 - 25 - 0 - 13 - 3 - 3 - 13 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns symbol parameter note max unit min max min t wcs 0 - 0 - t wch 10 - 15 - t wp 10 - 10 - t rwl 15 - 18 - t cwl 15 - - 18 t ds 0 - - 0 t d h 10 - - 15 15,23 write command setup time write command hold time write command pulse width write command to ras lead time write command to cas lead time data-in setup time data-in hold time 14,21 gm71v(s)18160 c/cl-6 gm71v(s)18160 c/cl-7 ns min 0 - - 8 - - - 0 - - max gm71v(s)18160 c/cl-5 ns ns ns ns ns ns 8 13 13 8 21 23 15,23 access time from ras access time from cas access time from address read command setup time read command hold time to cas access time from oe read command hold time to ras column address to ras lead time output buffer turn-off time column address to cas lead time cas to output in low-z output buffer turn-off time to oe output data hold time output data hold time from oe cas to d in delay time
gm71vs18160cl gm71v18160c rev 0.1 / apr ? 01 read- modify-write cycle refresh cycle symbol parameter note max unit min max min t pc 40 - 45 - ns t rasp ns t acp 35 - 40 - ns t rhcp ns 9,17,22 - - 16 100,000 100,000 - - 35 40 gm71v(s)18160 c/cl-6 gm71v(s)18160 c/cl-7 fast page mode cycle access time from cas precharge ras hold time from cas precharge fast page mode ras pulse width fast page mode cycle time symbol parameter note max unit min max min t rwc 155 - 181 - t rwd 85 - 98 - t cwd 40 - 46 - t awd 55 - 63 - 14 14 14 t oeh 15 - 18 - read-modify-write cycle time ras to we delay time cas to we delay time column address to we delay time oe hold time from we gm71v(s)18160 c/cl-6 gm71v(s)18160 c/cl-7 ns ns ns ns ns min 131 - 73 - 36 - 48 - 13 - max gm71v(s)18160 c/cl-5 symbol parameter note max unit min max min t csr 5 - 5 - ns t chr 10 - 10 - ns t rpc 5 - 5 - ns cas setup time (cas-before-ras refresh cycle) cas hold time (cas-before-ras refresh cycle) ras precharge to cas hold time gm71v(s)18160 c/cl-6 gm71v(s)18160 c/cl-7 min 5 - 8 - 5 - gm71v(s)18160 c/cl-5 max min 35 - 30 - - - 30 gm71v(s)18160 c/cl-5 max 100,000 21 22 21 fast page mode read-modify-write cycle symbol parameter note max unit min max min t prwc 85 - 96 - ns t cpw 60 - 68 - ns 14,22 fast page mode read-modify-write cycle time we delay time from cas precharge gm71v(s)18160 c/cl-6 gm71v(s)18160 c/cl-7 gm71v(s)18160 c/cl-5 max min 76 - 53 -
gm71vs18160cl gm71v18160c rev 0.1 / apr ? 01 self refresh mode symbol parameter note max unit min max min t rass ras pulse width(self-refresh) 100 - 100 - t rps ras precharge time(self-refresh) 110 - 130 - ns t chs cas hold time(self-refresh) -50 - -50 - ns gm71vs18160 cl-6 gm71vs18160 cl-7 us max min 100 - 90 - -50 - gm71vs18160 cl-5 26 notes: 1. ac measurements assume tt = 5ns. 2. an initial pause of 200us is required after power up followed by a minimum of eight initialization cycles(any combination of cycles containing ras-only refresh or cas-before-ras refresh). if the internal refresh counter is used, a minimum of eight cas-before-ras refresh cycles are required. 3. operation with the t rcd (max)limit insures that trac (max)can be met, trcd (max)is specified as a reference point only; if t rcd >= t rad (max) + t aa (max) - t cac (max), then access time is controlled exclusively by t cac . 4. operation with the t rad (max) limit insures that t rac (max)can be met, t rad (max)is specified as a reference point only; if t rad is greater than the specified t rad (max)limit, then access time is controlled exclusively by t aa . 5. either t odd or t cdd must be satisfied. 6. either t dzo or t dzc must be satisfied. 7. v ih (min) and v il (max) are reference levels for measuring timing of input signals. also, transition times are measured between v ih (min) and v il (max). 8. assumes that t rcd <= t rcd (max) and t rad <= t rad (max). if t rcd or t rad is greater than the maximum recommended value shown in this table, trac exceeds the value shown. 9. measured with a load circuit equivalent to 2 ttl load and 100pf. 10. assumes that t rcd >= t rcd (max) and t rcd + t cac (max) >= t rad + t aa (max). 11. assumes that t rad >= t rad (max) and t rcd + t cac (max) <= t rad + t aa (max). 12. either t rch or t rrh must be satisfied for a read cycles. 13. t off (max) and t oez (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t wcs , t rwd , t cwd , t awd and t cpw are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only; if t wcs >= t wcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle ; if t rwd >= t rwd (min), t cwd >= t cwd (min), and t awd >= t awd (min), or t cwd >= t cwd (min), t awd >= t awd (min) and t cpw >= t cpw (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of data out (at access time)is indeterminate.
gm71vs18160cl gm71v18160c rev 0.1 / apr ? 01 15. these parameters are referred to ucas and lcas leading edge in early write cycles and to we leading edge in delayed write or read-modify-write cycles. 16. t rasp defines ras pulse width in fast page mode cycles. 17. access time is determined by the longest among t aa , t cac ,and t acp . 18. in delayed write or read-modify-write cycles, oe must disable output buffer prior to applying data to the device. after ras is reset, if t oeh >= t cwl , the i/o pin will remain open circuit (high impedance); if t oeh < t cwl , invalid data will be out at each i/o. 19. when both ucas and lcas go low at the same time, all 16-bit data are written into the device. ucas and lcas cannot be staggered within the same write/read cycles. 20. all the v cc and v ss pins shall be supplied with the same voltages. 21. t asc , t cah , t rcs , t wcs , t wch , t csr and t rpc are determined by the earlier falling edge of ucas or lcas. 22. t crp , t chr , t rch , t acp and t cpw are determined by the later rising edge of ucas or lcas. 23. t cwl , t dh , t ds and t csh should be satisfied by both ucas and lcas. 24. t cp is determined by that time the both ucas and lcas are high. 25. when output buffers are enabled once, sustain the low impedance state until valid data is obtained. when output buffer is turned on and off within a very short time, generally it causes large v cc /v ss line noise, which causes to degrade v ih min/v il max level. 26. please do not use t rass timing, 10us <= t rass <= 100us. during this period, the device is in transition state from normal operation mode to self refresh mode. if t rass >= 100us, then ras precharge time should use t rps instead of t rp . 27. h or l (h: v ih (min) <= v in <= v ih (max), l: v il (min) <= v in <= v il (max))
gm71vs18160cl gm71v18160c rev 0.1 / apr ? 01 package dimension 42 soj unit: inches (mm) 0.405(10.29) max 0.394(10.03) min 0.455(11.56) min 0.471(11.96) max 0.017(0.45) max 0.012(0.30) min typ 0.031(0.80) 0.830(21.08) max 0.820(20.82) min 0.047(1.20) max 0.006(0.15) max 0.002(0.05) min 0.041(1.05) max 0.037(0.95) min 0.024(0.60) max 0.016(0.40) min 0.008(0.21) max 0.004(0.12) min 0 ~ 5 ? 1.072(27.23) max 0.395(10.03) min 0.435(11.06) min 0.445(11.30) max 0.148(3.75) max 0.128(3.25) min 0.026(0.66) min typ 0.050(1.27) 0.405(10.29) max 0.020(0.50) max 0.015(0.38) min 1.058(26.89) max 0.360(9.15) min 0.380(9.65) max 0.025(0.64) min 0.093(2.38) min 0.032(0.81) max 44(50) tsop i
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